1. Field of the Invention
This invention relates to an output circuit for outputting a signal to an external circuit, and more particularly to a semiconductor integrated circuit with such an output circuit built-in.
2. Related Art
Interface signals are available at very high speed in recent years, and measures to cope with interface signal noise and EMI (electromagnetic interference) have been needed. As a countermeasure for such noise and EMI, there is implemented a measure to reduce an amplitude of an interface signal. However, as described in Japanese Published Patent No. Hei-6-326591 (Page 1, FIG. 1), when the amplitude of a signal is lowered by reducing a source voltage supplied to an output circuit, a power circuit becomes complicated. Further, there is a risk that reference levels of signals between a circuit of a high source voltage type and a circuit of a low source voltage type may not be in agreement.
Furthermore, there is a case where a differential signal is used as an interface signal. FIG. 18 is a diagram showing an example of a prior art differential signal output circuit. A differential signal output circuit 81 shown in FIG. 18 is a circuit for outputting, based on one input signal J1, a pair of differential signals of a first output signal J4 and a second output signal J4 bar. However, in the differential signal output circuit 81, a drive signal J3 is delayed from a drive signal J2 by a delay time of an inverter INV 82, hence, the first output signal J4 and the second output signal J4 bar have skewing.
A differential signal output circuit capable of reducing the skewing mentioned above is also used. FIG. 19 is a diagram showing another example of a conventional differential signal output circuit. A differential signal output circuit 91 shown in FIG. 19 is a circuit for outputting, based on one input signal K1, a pair of differential signals of a first output signal K4 and a second output signal K4 bar. The interface signal output circuit 91 is, by comparison to the interface signal output circuit 81 (refer to FIG. 1), further constituted by a capacitor C91, and by this capacitor C91, a drive signal K2 is delayed to reduce skewing of drive signals K2 and K3, thereby decreasing skewing of the first output signal K4 and the second output signal K4 bar.
Nevertheless, in the interface signal output circuit 91, due to a scattering of a manufacturing process, an electrostatic capacity required to reduce the skewing of the first output signal K4 and the second output signal K4 bar may not be in agreement with an electrostatic capacity of the capacitor C91. As a result, there were cases where yield dropped or a product defect occurred at a client's side. Also, it was necessary to be stringent about allowing margins of a source potential fluctuation and a temperature fluctuation, sometimes leading to a yield drop.
In view of the above-mentioned considerations, it is a first object of this invention to make high-speed operation possible through a simple circuit configuration in an output circuit for outputting signals of a small amplitude. Further, it is a second object of this invention to prevent a yield drop and the like in a differential signal output circuit for outputting a pair of differential signals. Still further, it is a third object of this invention to provide a semiconductor integrated circuit having such an output circuit built-in.